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MC14060B 14-Bit Binary Counter and Oscillator
The MC14060B is a 14-stage binary ripple counter with an on-chip oscillator buffer. The oscillator configuration allows design of either RC or crystal oscillator circuits. Also included on the chip is a reset function which places all outputs into the zero state and disables the oscillator. A negative transition on Clock will advance the counter to the next state. Schmitt trigger action on the input line permits very slow input rise and fall times. Applications include time delay circuits, counter controls, and frequency dividing circuits. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
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16 PDIP-16 P SUFFIX CASE 648 MC14060BCP AWLYYWW 1
16 SOIC-16 D SUFFIX CASE 751B 1 16 TSSOP-16 DT SUFFIX CASE 948F 1 14 060B ALYW 14060B AWLYWW
* * * * * * * *
Fully Static Operation Diode Protection on All Inputs Supply Voltage Range = 3.0 V to 18 V Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range Buffered Outputs Available from Stages 4 Through 10 and 12 Through 14 Common Reset Line Pin-for-Pin Replacement for CD4060B Pb-Free Packages are Available*
Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 1) Ambient Temperature Range Storage Temperature Range Lead Temperature (8 Second Soldering) Value -0.5 to +18.0 -0.5 to VDD +0.5 10 500 -55 to +125 -65 to +150 260 Unit V V mA mW C C C A WL, L YY, Y WW, W
16 SOEIAJ-16 F SUFFIX CASE 966 1 = Assembly Location = Wafer Lot = Year = Work Week MC14060B ALYW
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Temperature Derating: Plastic "P and D/DW" Packages: -7.0 mW/C from 65C To 125C. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2004
1
July, 2004 - Rev. 6
Publication Order Number: MC14060B/D
MC14060B
Q12 Q13 Q14 Q6 Q5 Q7 Q4 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q10 Q8 Q9 RESET CLOCK OUT 1 OUT 2 H X = Don't Care
Table 1. Truth Table
Clock Reset L L H Output State No Change Advance to Next State All Outputs are Low
Figure 1. Pin Assignment
9 10 11
OUT 2 OUT 1 CLOCK C C Q Q C C Q Q Q4 7 C C Q Q Q5 5 C C Q Q Q12 1 C C Q Q Q13 2 C C Q Q Q14 3
R
R
R
R
R
R
12
RESET Q6 = PIN 4 Q7 = PIN 6 Q8 = PIN 14 Q9 = PIN 13 Q10 = PIN 15 VDD = PIN 16 VSS = PIN 8
Figure 2. Logic Diagram
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2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 3. The formulas given are for the typical characteristics only at 25C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.002.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Symbol
IT
IDD
Cin
Iin
IOL
IOH
VIH
VIL
VIH
VIL
VOH
VOL
Total Supply Current (Notes 3, 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching)
Quiescent Current (Per Package)
Input Capacitance (Vin = 0)
Input Current
Output Drive Current (VOH = 2.5 V) (Except Source Pins 9 and 10) (VOH = 4.6 V) (VOH = 9.5 V) (VOH = 13.5 V)
Input Voltage (VO = 4.5 Vdc) (VO = 9.0 Vdc) (VO = 13.5 Vdc)
Input Voltage (VO = 4.5 or 0.5 V) (VO = 9.0 or 1.0 V) (VO = 13.5 or 1.5 V)
Output Voltage Vin = VDD or 0
(VOL = 0.4 V) (VOL = 0.5 V) (VOL = 1.5 V)
(VO = 0.5 Vdc) (VO = 1.0 Vdc) (VO = 1.5 Vdc)
(VO = 0.5 or 4.5 V) (VO = 1.0 or 9.0 V) (VO = 1.5 or 13.5 V)
Vin = 0 or VDD
Characteristic
"0" Level (For Input 11 and Output 10)
"1" Level
"0" Level
"1" Level
"1" Level
"0" Level
Sink
VDD
Vdc
5.0 10 15
5.0 10 15
5.0 10 15
5.0 5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
15
-
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-3.0 -0.64 -1.6 - 4.2 4.95 9.95 14.95
MC14060B
4.0 8.0 12.5
0.64 1.6 4.2
3.5 7.0 11.0
Min
- - -
-
-
- - -
- - -
- - -
- 55C
3 0.1 0.05 0.05 0.05 Max 5.0 10 20 1.0 2.0 2.5 1.5 3.0 4.0 - - - - - - - - - - - - - - - - - -2.4 -0.51 -1.3 -3.4 4.95 9.95 14.95 4.0 8.0 12.5 0.51 1.3 3.4 3.5 7.0 11.0 Min IT = (0.25 mA/kHz) f + IDD IT = (0.54 mA/kHz) f + IDD IT = (0.85 mA/kHz) f + IDD - - - - - - - - - - - - - - 25C Typ (Note 2) -4.2 -0.88 -2.25 -8.8 0.005 0.010 0.015 0.88 2.25 8.8 2.75 5.50 8.25 2.25 4.50 6.75 2.75 5.50 8.25 2.25 4.50 6.75 5.0 5.0 10 15 0 0 0 - - - - - - - - - - - - - - - - 0.00001III - 0.1III 1.0 0.05 0.05 0.05 Max 5.0 10 20 7.5 1.0 2.0 2.5 1.5 3.0 4.0 - 1.7 - 0.36 - 0.9 - 2.4 4.95 9.95 14.95 4.0 8.0 12.5 0.36 0.9 2.4 3.5 7.0 11.0 Min - - - - - - - - - - - - - 125C 0.05 0.05 0.05 Max 150 300 600 1.0 2.0 2.5 1.5 3.0 4.0 - - - - - - - - - - - - - - - - - Unit Vdc Vdc mA mA mA mA mA V V V V pF
II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I III I I I I I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII III I I I I IIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I III I I I I IIIII IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
5. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25C)
tPHL
tw
tTLH tTHL
ff
twH
tPLH tPHL
tTHL
tTLH
CLOCK
Symbol
PULSE GENERATOR
Figure 1. Power Dissipation Test Circuit and Waveform
Propagation Delay Time Reset to On
Reset Pulse Width
Clock Rise and Fall Time
Clock Pulse Frequency
Clock Pulse Width
Propagation Delay Time Clock to Q4
Output Fall Time (Counter Outputs)
Output Rise Time (Counter Outputs)
500 mF
Clock to Q14
CLOCK
50% DUTY CYCLE
90% 50% 10%
NC NC
20 ns
Q4 OUT1 Q5 OUT2 Qn R
ID
VDD
VSS
Characteristic
20 ns
0.01 mF
CL
CL
VDD
VSS
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CL
MC14060B
4 PULSE GENERATOR VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15
Figure 2. Switching Time Test Circuit and Waveforms
CLOCK tTLH Q Min 120 60 40 100 40 30 - - - - - - - - - - - - - - - - - - CLOCK 20 ns NC NC 90% 50% 10% tPLH Q4 OUT1 Q5 OUT2 Qn R No Limit Typ (Note 5) 170 80 60 415 175 125 90% 50% 10% 1.5 0.7 0.4 VDD 5 14 17 40 15 10 65 30 20 50 30 20 40 25 20 VSS tWH Max 350 160 100 740 300 200 200 100 80 200 100 80 CL 3.5 8 12 2.7 1.3 1.0 tTHL
- -
-
- - -
tPHL 20 ns CL MHz Unit ns ns ns ns ns ns ns ms CL
MC14060B
11 f[ RESET 10 Rtc RS Ctc OUT 1 9 OUT 2 1 2.3 RtcCtc
if 1 kHz f 100 kHz and 2Rtc < RS < 10Rtc (f in Hz, R in ohms, C in farads) The formula may vary for other frequencies. Recommended maximum value for the resistors in 1 MW.
Figure 3. Oscillator Circuit Using RC Configuration
TYPICAL RC OSCILLATOR CHARACTERISTICS
8.0 FREQUENCY DEVIATION (%) 4.0 0 - 4.0 - 8.0 - 12 1.0 V f, OSCILLATOR FREQUENCY (kHz) VDD = 15 V 100 50 20 10 5 2 1 0.5 0.2 0.1 1.0 k 0.0001 10 k 100 k RTC, RESISTANCE (OHMS) 0.001 0.01 C, CAPACITANCE (mF) 1.0 M 0.1 f AS A FUNCTION OF C (RTC = 56 kW) (RS = 120 k) VDD = 10 V f AS A FUNCTION OF RTC (C = 1000 pF) (RS 2RTC)
5.0 V
RTC = 56 kW C = 1000 pF RS = 0, f = 10.15 kHz @ VDD = 10, TA = 25C RS = 120 kW, f = 7.8 kHz @ VDD = 10 V, TA = 25C
- 16 - 55
- 25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
Figure 4. RC Oscillator Stability
Figure 5. RC Oscillator Frequency as a Function of RTC and C
CLOCK 11 RESET 18M RO CS CT
10 OUT 1
9 OUT 2
Figure 6. Typical Crystal Oscillator Circuit
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I I IIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIII II I II II I I IIIIIIIIIIIIIIII IIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIII II I II II I I IIIIIIIIIIIIIIII IIIIIIIIIIIIIII I IIIIIIIIIIIIIIII II I II II I I IIIIIIIIIIIIIIII IIIIIIIIIIIIIII II IIIIIIIIIIIIIIII IIIIII II IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIII IIIIIIIIIIIIIIII
Table 2. Typical Data for Crystal Oscillator Circuit
Characteristic 500 kHz 32 kHz Circuit Circuit Unit 500 1.0 47 82 20 32 6.2 kHz kW kW pF pF Crystal Characteristics Resonant Frequency Equivalent Resistance, RS External Resistor/Capacitor Values RO CT CS 750 82 20 Frequency Stability Frequency Changes as a Function of VDD (TA = 25C) VDD Change from 5.0 V to 10 V VDD Change from 10 V to 15 V Frequency Change as a Function of Temperature (VDD = 10 V) TA Change from - 55C to + 25C Complete Oscillator (Note 6) TA Change from + 25C to + 125C Complete Oscillator (Note 6) +6.0 +2.0 +2.0 +2.0 ppm ppm ppm ppm +100 -160 +120 -560 6. Complete oscillator includes crystal, capacitors, and resistors.
MC14060B
ORDERING INFORMATION
Device MC14060BCP MC14060BCPG MC14060BD MC14060BDR2 MC14060BDR2G MC14060BFEL MC14060BDTR2 Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 SOIC-16 SOIC-16 (Pb-Free) SOEIAJ-16 (Pb-Free) TSSOP-16 (Pb-Free) Shipping 500 Units / Rail 500 Units / Rail 48 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 2000 / Tape & Reel 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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MC14060B
PACKAGE DIMENSIONS
PDIP-16 P SUFFIX CASE 648-08 ISSUE T
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
-A-
16 9
SOIC-16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC14060B
PACKAGE DIMENSIONS
TSSOP-16 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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EEE CCC EEE CCC
9
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
MC14060B
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O
LE Q1 E HE
1 8
16
9
M_ L DETAIL P
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC14060B
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC14060B/D

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